A speed controlling system of a digital type for a rotating body has been often used in a magnetic record reproducing system.
Hereinafter will be described an operation of a rotational speed controlling system of a capstan motor in the magnetic record reproducing system.
A sinusoidal wave signal is outputted from a frequency generator attached to a motor. This signal has a cycle depending on a rotational speed of the motor. This signal is amplified and shaped by a FG signal amplifier to be a square wave signal. An output of the FG signal amplifier is inputted to a speed error detector and the cycle of the inputted signal is quantized by a counter. A subtracter subtracts reference cycle data outputted from a reference value generator from the quantized count value, and a speed error is outputted therefrom. The detected speed error is compensated in relation with a gain in a speed controlling region by a digital filter, then is inputted into a D/A converter. An output from the D/A converter is supplied to a motor driving circuit to control a speed of the motor.
Next description will be on a control limit frequency in a speed controlling system for a rotating body, by representing each block in the above structure by transfer functions.
A transfer function of a motor is represented by a torque constant Kt (g-cm/A), a moment of inertia (g-cm.sec.sec/rad) and a Laplacian operator s. A rotational speed of the motor is converted into a speed detecting signal by a frequency generator having teeth of the number z per one rotation, and a cycle of the inputted signal is measured by an input-output sampler, a counter and a shift averaging element.
Supposing that a frequency of a reference clock supplied to the counter is Fck (Hz) and a sampling cycle is T (sec), a transfer function of the counter is given by a formula: ##EQU1##
A measured cycle value of the speed detecting signal quantized by the counter is subtracted a reference value to calculate a speed error. The calculated speed error is inputted to the digital filter having a transfer function Gf to be compensated in relation with a gain in a speed controlling area, then is supplied to a zero-order holder made up of an input buffer of the D/A converter.
A transfer function Gh of the zero-order holder is given by a formula: ##EQU2##
An output of the zero-order holder is converted into an analogue voltage by the D/A converter having a conversion gain Kx and is supplied to a motor driving circuit having a transfer conductance gm (A/V). The output current from the motor driving circuit controls a speed of the motor.
The conversion gain Kx of the D/A converter is given by a formula: ##EQU3## where n: number of conversion bit; and
Vcc: a supplied voltage.
In the above transfer functions of the respective part, phase characteristics of the counter part and the holder depend on the sampling cycle T. The phase characteristics .theta.c and .theta.h of the counter part and the holder at an arbitrary frequency are respectively given on the basis of the formulae (1) and (3) by formulae: EQU .theta.=.pi..multidot.f.multidot.T (5) EQU .theta.h=.pi..multidot.f.multidot.T (6)
By the way, a stable operation of the controlling system requires, in general, a phase margin from 40 to 60 degrees in a frequency at which a gain of an open loop is 0 dB. However, an inertial term in an inertial block at that frequency becomes dominant so that a phase delay of 90 degrees occurs at that frequency. Therefore, required conditions to obtain a phase margin of 60 degrees at that frequency are given by the following formula: ##EQU4##
Under the conditions, a control limit frequency Flim stably controllable the motor is represented using a FG frequency Ffg by a formula: ##EQU5##
As having been described, the control limit frequency stably controllable the motor is limited by the FG frequency. A multiplying circuit is provided to the speed error detector before inputting a speed detecting signal to reduce the sampling cycle to a half, thereby expanding the control limit frequency FG up to 1/6 of the FG frequency.
In order to employ the multiplying method, it is, however, necessary that a period of time of one cycle of the speed detecting signal is equal to or longer than twice a time period required from the detection of speed error to the outputting to the D/A converter.
In other words, in case that the FG frequency is relatively high, a limit value of the control limit frequency is theoretically 1/12 of the FG frequency as shown by the formula (8).
In the commercial VTR or the like, a direct driving system has been often used as a driving system for a capstan motor. However, torque ripples of the motor cause irregularity in rotation and wow and flutter are thus worsened.
The torque ripples depend on one rotational cycle of the motor and have typically a harmonic element of integral multiples of the rotational cycle.
As a method for removing the torque ripples depending on a rotational cycle of a motor by utilizing this peculiar property, there is reported an example where a repeated control (or a learning control) is employed ("System and Control", Vol. 30, No. 1, P34-41, 1986).
The control method employed a repeated control is effective to remove the torque ripples depending on a rotational cycle of a motor, but requires a lot of memories or shift registers to accomplish a learning mechanism and further a compensator made up of a complex higher grade filter or the like to obtain stability in the control system. It is, thus, costly to perform the repeated control method in the conventional system.
An object of the present invention is to overcome the above problems and, therefore, to provide a speed controlling system enabling a stable speed control even if the multiplying method is unadoptable therein.